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sThe present invention relates to self-aligned gate structures, and more particularly to the use of a polysilicon spacer as a self-aligned gate structure for field effect transistors (FETs).
In the formation of semiconductor devices, after the individual devices such as the transistors have been formed in a silicon substrate, they must be connected together to perform the desired circuit functions. This interconnection process is generally called “metallization” and is performed using a number of different photolithographic, deposition, and removal techniques.
Presently, the most common metal interconnection for the sub-micron scale integrated circuits is aluminum. However, as the size of the aluminum interconnections are reduced, the aluminum films are more difficult to use in sub-micron technology. In the past, aluminum was preferred since it could be patterned with high resolution and fast (dry) etch processes. These processes enable the fine line patterning that is required for the sub-micron interconnection technology.
As interconnection sizes are reduced, aluminum presents problems such as increasing resistivity

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